1. Field of the Invention
The present invention relates to a semiconductor device having a lateral high breakdown voltage element, and more specifically, to a semiconductor device having a lateral high breakdown voltage element with an SOI (Semiconductor on Insulator) structure and capable of maintaining a high breakdown voltage.
2. Description of the Background Art
First, a conventional technique will be described.
FIG. 36 is a schematic cross sectional view showing a first example of a conventional semiconductor device. With reference to FIG. 36, the semiconductor device is provided with an insulation substrate 103. An n.sup.- semiconductor layer 102 (referred to as an SOI layer) is formed on insulation substrate 103. An n.sup.+ semiconductor region 104 with low resistance is formed in the surface of n.sup.- semiconductor layer 102. A p.sup.+ semiconductor region 105 is formed to surround the n.sup.- semiconductor layer 102. A cathode electrode 106 is electrically connected to n.sup.+ semiconductor region 104. An anode electrode 107 is electrically connected to p.sup.+ semiconductor region 105. A back electrode 108 is formed on the back surface of insulation substrate 103. An insulation film 109 is provided in n.sup.- semiconductor layer 102 for electrically isolating n.sup.- semiconductor layer 102 to provide a plurality of portions. An insulation layer 111 is provided on n.sup.- semiconductor layer 102 for electrically isolating cathode and anode electrodes 106 and 107 from other portions.
The operation of the semiconductor device will now be described.
With reference to FIG. 37, when anode and back electrodes 107 and 108 are at 0V and + voltage is applied to cathode electrode 106, a depletion layer 133 extends from a pn junction between n.sup.- semiconductor layer 102 and p.sup.+ semiconductor region 105. The extension of depletion layer 133 stops when it reaches n.sup.+ semiconductor region 104. Depletion layer 133 is a kind of insulator, allowing no current flow between cathode and anode electrodes 106 and 107. Such a semiconductor device is referred to as a diode.
Furthermore, addition of an insulation gate structure to this structure enables fabrication of a self-arc-extinguishing device such as an MOS (Metal Oxide Semiconductor) transistor, an IGBT (Insulated Gate Bipolar Transistor) or the like. It is noted that voltage is not allotted to insulation layer 103 in the above structure.
N.sup.- semiconductor layer 102 must be large to retain the major part of electric field in order to achieve higher breakdown voltage with a semiconductor device having the above structure. While horizontal (normal to the sheet of drawings) extension of the layer can be relatively readily achieved, vertical (longitudinal direction in the drawings) extension disadvantageously expands the isolation region as large thickness t.sub.soi of the SOI layer is required, making techniques for isolation and burying difficult.
FIG. 38 is a schematic cross sectional view showing a second example of a conventional semiconductor device. With reference to FIG. 38, n.sup.- semiconductor layer 102 is formed on a semiconductor substrate 101 with a buried insulation layer 103 formed of an oxide film interposed. Since other members in the drawing are almost the same as those for the conventional semiconductor device shown in FIG. 36, the same or corresponding portions have the same reference numerals and description thereof will not be repeated here.
The operation will now be described.
With reference to FIG. 39, when anode and back electrodes 107 and 108 are at 0V and + voltage is applied to cathode electrode 106, a depletion layer A extends from a pn junction between n.sup.- semiconductor layer 102 and p.sup.+ semiconductor region 105. At the time, semiconductor substrate 101 is generally at 0V and functions as a field plate through buried insulation layer 103, so that a depletion layer B extends from the interface between n.sup.- semiconductor layer 102 and buried insulation layer 103 toward the surface of n.sup.- semiconductor layer 102 in addition to the above mentioned depletion layer A. On the other hand, the electric field at the pn junction between n.sup.- semiconductor layer 102 and p.sup.+ semiconductor region 105 is reduced as depletion layer B facilitates the extension of depletion layer A.
The effect is generally called RESURF (Reduced Surface Field) effect, and it is described in J. A. Appels et al., "HIGH VOLTAGE THIN LAYER DEVICES (RESURF DEVICES)", IEEE IEDM Tech. Dig., 1979, pp. 238-241 that extending the pn junction along the interface rather than buried insulation layer 103 provides a similar effect.
In the above structure, a ratio of divided voltage per unit thickness of oxide film to silicon is that of a reciprocal of their dielectric constants (.di-elect cons..sub.oxi =3.9, .di-elect cons..sub.si =11.7), that is, about 3:1. Thus, breakdown voltage can be increased by increasing the thickness of buried oxide film 3 retaining a considerable part of voltage.
This is shown FIG. 40. RESURF effect is effective in the region where breakdown voltage increases with thickness. As the thickness of a film is simply increased, breakdown voltage (BV) reversely begins to decrease at a certain value. This is because the amount of extension for depletion layer B decreases as it is away from the ground voltage of semiconductor substrate 101 assisting the extension of depletion layer B, thereby undermining electric field reduction effect for depletion layer A. Accordingly, the thickness of the buried oxide film must be around 7 .mu.m to achieve as high a breakdown voltage as 600V. In a film formation method, however, the formation of such a film with thickness of around 7 .mu.m disadvantageously increases cost as considerably long processing time is required as shown in FIG. 41.
A technique disclosed in Japanese patent Laying-Open No. 7-183522 will now be described as a conventional example for forming the thinnest possible buried oxide film while maintaining high breakdown voltage.
FIG. 42 is a schematic cross sectional view showing a structure of a semiconductor device disclosed in the aforementioned laid open application. With reference to FIG. 42, a semiconductor layer 102 is formed on a semiconductor substrate 101 with a buried insulation layer 103 interposed. A field oxide film layer 111b and an LDMOS transistor are formed in the surface of semiconductor layer 102.
The LDMOS transistor includes a channel region 105a, a source region 105b, a drain region 104, a drift region 120, a gate oxide insulation layer 111a and a gate electrode layer 112. Channel region 105a is formed on one side of field oxide film layer 111b, whereas source region 105b is positioned in the surface of channel region 105a. Drain region 104 is positioned in the surface on the side opposite to source region 105b with field oxide insulation layer 111a sandwiched.
Gate electrode layer 112 is formed on channel region 105a with gate oxide insulation layer 111a therebetween and extends over field oxide layer 111b.
Drift region 120 is formed from the bottom surface of field oxide insulation layer 111a to that of semiconductor layer 102 and toward the side of drain region 104 from that of source region 105b, and formed of SiC (Silicon Carbide), for example.
In addition, a source electrode 107 and a drain electrode 106 are formed to be electrically connected to source and channel regions 105b and 105a as well as drain region 104, respectively.
An SiC layer used for drift region 120 does not exert any influence specific to SiC in chemical treatment, photolithography and implantation diffusion steps for the surface of SOI layer, thereby allowing fabrication of a device directly using a standard Si process.
SiC has a wider band gap than Si (Silicon), the material used for forming the semiconductor layer. Thus, replacing Si by SiC can enhance avalanche electric field strength, thereby increasing breakdown voltage without increasing the thickness of buried isolation layer 103.
In this structure, however, a gate is formed offset, and therefore laterally applied voltage V concentrates in a short distance W.sub.1 between gate electrode layer 122 and drain electrode 106, increasing electric field strength. This is shown by the equipotential line and electric field strength distribution in FIGS. 43A and 43B. It is noted that FIG. 43B shows the electric field strength distribution in the surface portion of SOI layer 102 along the line XLIIIB--XLIIIB in FIG. 43A.
With reference to FIGS. 43A and 43B, avalanche electric field strength is more easily attained when electric field strength E is increased. If avalanche electric field strength is attained in the surface portion of SOI layer 102, breakdown voltage can not effectively be enhanced even when the bottom portion of the SOI layer is formed of an SiC layer. Therefore, the effect of offset can be achieved only in a limited region having relatively low breakdown voltage, which is capable of retaining the concentrated electric field in the surface by means of a field oxide film.
Further, distance W.sub.1 between gate electrode layer 112 and drain electrode 106 can be made longer to prevent the concentration of laterally applied voltage. In this case, electric field strength generally decreases as compared with FIG. 43B. Nevertheless, a high electric field region is likely to be formed locally in the opposite ends R and electric field strength peak P is in the high electric field region. Electric field strength E in the peak portion P is therefore likely to attain avalanche electric field strength, and once avalanche electric field strength is attained, breakdown voltage cannot effectively be increased as mentioned in the foregoing.
A combination of parameters required for a substrate (thickness and resistance values of SOI layer, thickness of buried insulation layer or the like) can be optimized to decrease the peak value. This may however result in disadvantageous introduction of new rate-limiting factors.